The present invention relates to a method of fabricating an insulated gate semiconductor device or an integrated circuit comprising a multiplicity of insulated-gate semiconductor devices on an insulating substrate with a high production yield and also to a semiconductor device fabricated by such a method. Semiconductor devices according to the invention are used as thin-film transistors (TFTS) in a driver circuit for an active-matrix display such as a liquid crystal display, in a driver circuit for an image sensor, in an SOI integrated circuit, or in a conventional semiconductor integrated circuit (e.g., a microprocessor, a microcontroller, a microcomputer, a semiconductor memory, or the like). Furthermore, the invention relates to an integrated semiconductor device having an active-matrix in a broad sense (i.e., which comprises interconnections arranged in rows and columns, and in which a selecting circuit consisting of at least one transistor is disposed in each intersection) and a peripheral circuit for driving the active-matrix. In particular, the integrated semiconductor device comprises an active-matrix liquid-crystal display (AMLCD), DRAM, SRAM, EPROM, EEPROM, mask ROM, or other semiconductor integrated circuit formed on an insulating substrate.
In recent years, researches on formation of insulated-gate semiconductor devices (MOSFETs) on an insulating substrate have been earnestly conducted. Such formation of a semiconductor integrated circuit on an insulating substrate is advantageous for high-speed operation, for the following reason. The speed of the prior art semiconductor integrated circuit has been mainly restricted by the stray capacitance between each conductive interconnect and the substrate. On the other hand, such stray capacitance does not exist on an insulating substrate. A MOSFET formed on an insulating substrate and having an active layer in the form of a thin film is known as a thin-film transistor (TFT). In the prior art semiconductor integrated circuit, TFTs are used as load transistors for an SRAM, for example.
Recently, a commercial product comprising a semiconductor integrated circuit which is required to be formed on a transparent substrate has emerged. Examples of this product include circuits for driving optical devices such as liquid crystal displays and image sensors. TFTs are also used in these driver circuits. Since these circuits are required to be formed in a large area, there is a demand for a decrease in the temperature of the TFT fabrication process. Furthermore, where a device has numerous terminals on an insulating substrate, if the terminals must be connected with a semiconductor integrated circuit, one might consider to form the first stage of the semiconductor integrated circuit or the semiconductor integrated circuit itself on the same insulating substrate monolithically to increase the packaging density.
Conventionally, the crystallinity of TFTs has been improved by annealing an amorphous, semi-amorphous, or crystallite semiconductor film at a temperature of 450-1200xc2x0 C. Thus, a good semiconductor film, i.e., having sufficiently high mobilities, is obtained. Some amorphous TFTs comprise a semiconductor film made of an amorphous material. However, their mobilities are lower than 5 cm2/Vxc2x7s, normally as low as about 1 cm2/Vxc2x7s. Their operating speed and inability to fabricate P-channel TFTs have restricted their use severely. Anneal at the above-described temperature has been needed to obtain TFTs having mobilities exceeding 5 cm2/Vxc2x7s. Also, the anneal permitted fabrication of P-channel TFTs (PTFTs). These thermal annealing steps can be carried out by the use of irradiation of laser light or intense light.
However, it has been pointed out that these TFTs do not have sufficiently high reliability to be used in an active-matrix device because of large leakage current in OFF state. Accordingly, we have proposed improved methods as described in Japanese Patent application Ser. Nos. 34194/1992 and 30220/1992. Specifically, gate electrodes are made of a low-resistivity metal such as aluminum. The surface of each gate electrode is anodized so that the surface is coated with an oxide. Using this lamination of the metal and the oxide as a main mask, impurities are implanted to form an offset region. As a result, the leakage current is reduced. Also, the interlayer insulation is enhanced by the anodic oxide film. Consequently, short circuit at the crossing portions can be greatly reduced.
More specifically, the film of the anodic oxide has only a small number of pinholes and can withstand high voltages greater than 7 MV/cm. Hence, interlayer insulation is secured. In practice, we have succeeded in greatly reducing short circuit between interconnections, by utilizing the techniques described in the above-cited Japanese Patent application Ser. Nos. 34194/1992 and 30220/1992. This is quite important in active-matrix regions because interconnections cross each other at very numerous locations.
However, we have discovered that technically very difficult problems occur when one attempts to fabricate a device on which an active-matrix device and its peripheral driver circuit are monolithically formed (e.g., a memory or an AMLCD), using the above-described technique.
Generally, a peripheral circuit is complex in structure and has interconnects connected in a complex manner. Therefore, even if one attempts to coat metal electrodes with an anodic oxide, it is impossible to supply electric power because of the complexity of the interconnect structure. Also, if interconnects used only for supply of electric power are formed, then an extra photolithography step is necessary to remove these interconnects. This results in a decrease in the manufacturing yield. If a circuit is constructed together with these extra interconnects, then the device density is deteriorated severely.
In another proposed method, an anodic oxidation step is used to fabricate an active-matrix circuit portion. The anodic oxidation step is not employed when a peripheral circuit portion and other regions are formed. This method suffers from a very low production yield. It has been found that the main cause is the presence of numerous pinholes because the interlayer insulator is incomplete. The pinholes cause short circuits between an upper interconnect and a lower interconnect (i.e., a gate electrode and its interconnect).
This is an essential problem where interconnects of a metal having a low melting point are used. It is well known that aluminum and their alloys are excellent electrode materials. If impurity atoms are implanted into an active layer using gate electrodes made of such a material as a mask by a self-aligning process, then activation utilizing thermal annealing at a temperature of 630xc2x0 C. or higher cannot be adopted. Therefore, it is inevitable that a low-temperature activation technique such as laser annealing is used to activate the impurity atoms. Furthermore, a technique of forming an interlayer insulator film above 560xc2x0 C. cannot be adopted.
For example, an interlayer insulator material such as silicon oxide formed by LPCVD or atmospheric-pressure CVD at a substrate temperature above 560xc2x0 C. contains a quite small number of pinholes. Also, almost no short circuit occurs between interconnects. However, at low temperatures below 560xc2x0 C., only sputtering or plasma CVD can be used. In these methods, a large amount of dust is deposited onto the film during its growth. This increases the number of pinholes. Also, the resulting insulation is not satisfactory. Even in a peripheral driver circuit, interconnects cross each other. Therefore, in order to improve the production yield, there is a demand for a method of forming an anodic oxide with an improved production yield.
In view of the foregoing problems with the prior art techniques, the present invention has been made.
It is an object of the present invention to provide an optimum device structure and an optimum manufacturing process.
The techniques described in the above-cited Japanese Patent application Ser. Nos. 34194/1992 and 30220/1992 form an anodic oxide. As described in the patent specifications of these Japanese Patent applications, the greatest feature of these techniques is that when an inverse voltage is applied to each gate, the leakage current can be reduced greatly by the offset effect. This characteristic is necessary for TFTs in active-matrix regions which operate dynamically because of the necessity of holding pixel voltage with certainty. Also, the characteristic is necessary where the stand-by electric consumption of a flip-flop circuit should be suppressed. Therefore, where TFTs of this structure are used as pixel transistors of an AMLCD, as selecting transistors forming storage bits of a DRAM fabricated by SOI techniques, or as transistors forming an inverter circuit for the storage bits of an SRAM (especially a complete CMOS SRAM), great advantages can be obtained.
However, if peripheral circuits operate statically or partially statically, their leakage current presents no serious problems. Therefore, the circuits function satisfactorily even if an anodic oxide is not formed on the side surface, i.e., the offset structure is not adopted.
However, if a dense film as consisting of an anodic oxide is not formed on the top surface of the gate electrode, then leakage between interconnects greatly deteriorates the manufacturing yield. As described in the above-cited specifications, where laser annealing is utilized, the damage caused by the laser annealing step is minimized by the existence of an anodic oxide on the top surface of the gate electrode.
We know that a metal aluminum film fabricated by electron-beam evaporation has a flat surface and have submicrometer grain diameters. Therefore, the film well reflects light, especially UV light. After the film is directly irradiated with laser light, almost no damage was observed. However, after a film fabricated by sputtering or other similar method and having large grain sizes of about 1 xcexcm is directly irradiated with laser radiation, very large damage was observed. Since electron-beam evaporation is not adapted for mass production, the practical approach is to use sputtering techniques. That is, for a peripheral circuit, the gate electrode needs an anodic oxide not on its side surface but on its top surface.
Accordingly, in a semiconductor device of the present invention, TFTs in which almost no anodic oxide exists on the side surface of each gate electrode but an anodic oxide is formed only on the top surface are formed together with TFTs of active-matrix regions. TFTs of this structure and a device made up of these TFTs are fabricated in the manner described below.
A metal film made of, for example, aluminum is deposited on a semiconductor layer becoming islands and on a gate-insulating film. An oxide film is formed on the metal film by anodic oxidation. Although the preferred thickness range of the oxide film depends on the quality of the oxide film, we have found that where the thickness of the oxide is less than 30 nm, the composition deviates from the stoichiometric ratio, thus deteriorating the insulation. Therefore, the thickness of the insulator (the oxide) is preferably 30 nm or more. Since a very high voltage is applied to the device in order to form the oxide to a thickness of 300 nm or more by the anodic oxidation, it is not preferred that the oxide is formed to a thickness of 300 nm or more.
Then, the oxide and the metal film are etched to form gate electrodes of a desired shape. Thus, the anodic oxide is left on the top surfaces of the gate electrodes, and no anodic oxide exists on the side surfaces in the peripheral circuit. By the later ion implantation or doping, the gate electrode of the transistor in the peripheral circuit can be made self-aligned with at least one of source and drain of the transistor in the peripheral circuit.
The above-described etching process should be a directional etching process such as reaction ion etching (RIE). Where an isotropic etching process is carried out, voids (cusp) are created near the boundary because of the difference in etch rate between the anodic oxide and the metal film. As a result, the interconnects extending over the voids easily break. However, depending on the material, the whole process can not be effected by RIE.
As an example, where the metal material is aluminum, the anodic oxide is aluminum oxide but this cannot be removed by RIE. Therefore, in this case, the aluminum oxide film is first removed by wet etching. Then, using the remaining aluminum oxide as a mask, the metal aluminum is etched by RIE.
If it is impossible to employ RIE for etching of the metal aluminum and the process relies only on wet etching, then it is desired to make the metal aluminum film as thin as possible. More specifically, the ratio between the aluminum oxide film thickness and the metal aluminum film thickness should be less than 1:3. Preferably, the ratio is less than 1:2.
A monolithic matrix circuit is built, using these TFTs, in the manner described below. A first method comprises the following steps: (1) A metal film is formed in matrix regions as well as in a peripheral circuit; (2) This metal film is anodized to form an anodic oxide on the surface; (3) The anodic oxide is removed from unwanted locations; (4) Using the remaining anodic oxide as a mask, the metal film is etched, and gate electrodes are formed in the peripheral circuit and in the matrix regions; and (5) An electrical current is caused to flow through the matrix regions to form an anodic oxide only on the side surface of each gate electrode of the matrix regions.
We now take notice of the matrix regions fabricated by this method. First, the anodic oxide is formed by the step (2). The second anodization is effected by the step (5) while leaving the anodic oxide on the gate electrode. Therefore, a stress is induced between the initially formed anodic oxide and the anodic oxide formed later. This may peel off the initially formed anodic oxide.
This problem can be avoided by adding a step (4xe2x80x2) subsequently to the step (4) as shown in Example 1. This step (4xe2x80x2) consists of removing the anodic oxide from the matrix regions while masking only the peripheral circuit portion. By carrying out this step, the metal material of the gate electrodes of the matrix regions is fully exposed. Then, a uniform anodic oxide is formed on the top and side surfaces by the step (5). It is easy to mask only the matrix regions. The production yield is not deteriorated in spite of the addition of the step (4xe2x80x2). However, even the gate-insulating film may be etched away, depending on the kind of the etchant used. If the, semiconductor region surfaces are exposed, then the manufacturing yield will be deteriorated. Hence, care must be exercised. In any case, at least two anodization steps are necessary.
A second method according to the invention is the method of Example 2 and consists mainly of the following steps: (1) A metal film is deposited over the whole peripheral circuit portion, and a metal film is formed in the form of gate electrodes on the matrix regions; (2) An electrical current is caused to flow through the metal film on the peripheral circuit portion and through the gate electrodes and their interconnects of the matrix regions to form an anodic oxide; and (3) The anodic oxide and the metal film on the peripheral circuit portion are etched, and the gate electrodes of the peripheral circuit portion are formed.
This method involves only one anodization step but at least two photolithography steps are necessary in order to form the gate electrodes of the matrix regions and the gate electrodes of the peripheral circuit portion.
The impurities doped are activated in both the peripheral circuit and the active-matrix circuit by irradiating a laser light thereto.
Instead of this laser irradiation, a thermal annealing at 550xc2x0 C. or lower may be used to activate the impurities doped. Alternatively, the substrate may be heated at a temperature of 200 to 500xc2x0 C. during the laser irradiation. Further, these techniques may be combined. For example, the thermal annealing may be carried out after or before the laser irradiation. Further, the thermal annealings may be carried out twice, i.e. before and after the laser irradiation. The laser irradiation may be carried out maintaining the substrate substantially at room temperature. Alternatively, the laser irradiation may be carried out heating the substrate at a temperature of 200 to 500xc2x0 C.
It is necessary to control the substrate temperature of the heating in the laser irradiation or the thermal annealing in order to prevent the gate electrode material from being damaged. The present invention prevents hillock (abnormal crystal growth) from forming in a perpendicular direction even though the annealing is carried out at a relatively high temperature, since the anodic oxide film is formed on the top surfaces of the gate electrodes of both the peripheral circuit and the active-matrix circuit (i.e. the pixel transistor circuit). Accordingly, short circuit is hardly formed between layers.
Other objects and features of the invention will appear in the course of the description thereof, which follows.